The present invention relates to digital signal transmission systems particularly, but not exclusively, for use at high bit rates in the Gigabit per second range.
In digital transmission systems using transmission media such as coaxial cables and optical fibers it is necessary to regenerate the signal being transmitted at various intervals and ultimately to de-multiplex the signal at the terminus of the transmission medium. At bit rates up to 500 Megabits/second the signal regeneration can be carried out using known ECL logic families. However 500 Megabits/second represents the typical maximum switching speed for known ECL logic families and accordingly other techniques are necessary when working at higher bit rates.
It has now been realized that the regeneration of signals and demultiplexing of signals in the Gigabit/second range and below can be carried out using circuit techniques based on multiplexers, for example the multiplexer disclosed in FIG. 6 of British Patent Specification No. 1,552,739. The prior-art multiplexer shown in FIG. 6 of this British Patent is a synchronous digital multiplexer which uses a series gating technique. It produces a cyclic timing pulse of a desired period which is then applied in turn to a series of ECL gates. Each of these gates includes a pair of emitter-coupled transistors, with the cyclic timing pulse being applied to the common emitter connection. An input signal is applied to the base of a first emitter-coupled transistor in each pair while the base of the second transistor in each pair is connected to a source of reference voltage. The collector of each first transistor is connected to ground, while the collector of each second transistor is connected to a common output bus which is connected to an emitter-follower output transistor. The prior art multiplexer shown in FIG. 6 of the aforementioned British patent is a four-input-port multiplexer, and is thus suited for use in the digital signal transmission system of the present invention. However, as mentioned hereinafter, other suitable four-input-port multiplexers may be used, as the precise configuration of this prior-art component is not an essential feature of the invention. Since it is possible to switch a multiplexer on each zero crossover of a clock signal, the clock signal need only have a frequency of half that customarily necessary when using known ECL circuit elements such as decision circuits for retiming signals and demultiplexers which normally require a clock frequency the same as that of the bit rate. Consequently the known elements are inherently incapable of operating at a frequency in excess of 500 MHz.